An integrated circuit topography is a solution consisting in a spatial, freely expressed arrangement of elements and all or part of the connections of an integrated circuit, where at least one element is an active element. Thus, it is a three-dimensional structure of microelectronic semiconductor products presented in the form of a series of interrelated images, freely recorded or encoded.
An integrated circuit topography may be registered under the national procedure at the Polish Patent Office. It is also possible to obtain protection for such a solution in selected foreign countries.
We provide our Clients with expert comprehensive advice along with consultations helpful in obtaining the registration of an integrated circuit topography, and offer services of preparing documentation of the application and prosecuting the case before the Patent Office until the grant of the exclusive right is obtained.